A variety of isolation structures are presently used to fabricate semiconductor circuits. In one popular approach, shallow isolation structures are used to isolate adjacent electronic devices.
Shallow isolation structures may be fashioned using the LOCal Oxidation of Silicon (LOCOS) isolation approach. In the LOCOS process, a pad-oxide (SiO.sub.2) layer is first grown on the surface of a semiconductor substrate, followed by deposition of a silicon nitride (Si.sub.3 N.sub.4) layer over the pad-oxide layer. Using well-known techniques, these layers are patterned to define the width of the shallow recess to be etched into the substrate. Once the shallow recess has been etched, the substrate is subjected to an oxidation process whereby silicon dioxide (SiO.sub.2) is grown in the recess. The silicon nitride layer (which has not yet been removed) prevents any oxide growth over the substrate's surface. As a result, oxide grows to fill the entire recess, including the opening in the patterned oxide and silicon nitride layers which defined the width of the shallow recess.
Devices for preparing semiconductor wafers are known in the art. Wafer preparation includes slicing semiconductor crystals into thin sheets, and polishing the sliced wafers to free them of surface irregularities. In general, the polishing process is accomplished in at least two steps. The first step is rough polishing or abrasion. This step may be performed by an abrasive slurry lapping process in which a wafer mounted on a rotating carrier is brought into contact with a rotating polishing pad upon which is sprayed a slurry of insoluble abrasive particles suspended in a liquid. Material is removed from the wafer by the mechanical buffing action of the slurry. The second step is fine polishing. The fine polishing step is performed in a similar manner to the abrasion step. However, a slurry containing less abrasive particles is used. Alternatively, a polishing pad made of a less abrasive material may be used.
The fine polishing step often includes a chemical mechanical polishing ("CMP") process. CMP is the combination of mechanical and chemical abrasion, and may be performed with an acidic or basic slurry. Material is removed from the wafer due to both the mechanical buffing and the action of the acid or base.
The shallow trench isolation (STI) procedure provides an efficient means of producing integrated circuits in the sub- and sub-half micron regime. STI represents a vast improvement over the conventional LOCOS isolation technique. In the STI process, CMP is used to planarize the oxide to expose the nitride stop.
Advantages of the CVD oxide filled STI process include better device isolation, packing density and planarity. STI also eliminates the encroachment and stress problems associated with field oxide growth observed in the LOCOS isolation techniques. A key requirement of the STI process is planarization of CVD oxide to expose the nitride stop while controlling the relative heights of active and field areas. Final height of the field oxide must be higher than that of the active silicon under the nitride stop, but not high enough to produce a substantial step. This requirement poses a severe challenge for the planarization process.
STI planarization using CMP usually requires additional processing steps, thereby increasing the expense. Thus, an inexpensive one step CMP process would be desirable for STI planarization. The CMP process is known to provide excellent local planarity, but global planarity is affected by feature height, size, layout, density and polishing conditions such as mechanical polishing parameters, pad and slurry. An ideal planarization process would remove topography of different geometries simultaneously without dishing in wide low regions. However, current CMP process in STI applications causes dishing and damage to silicon in isolated regions making it unsuitable for production use. Dishing occurs because of longer polish time and pad deflection in the large field areas.
Various methods have been tried to reduce the dishing problem. Boyd and Ellul (J. M. Boyd, et al, Electochem. Soc. Proc., vol. 95-5, 1996, p. 290) reported the use of a thin nitride overcoat (40 nm) deposited on top of the gap filled oxide to reduce dishing. The nitride overcoat provides protection to the underlying oxide in low lying regions while the high level oxide is being polished at a much faster rate due to the oxide selectivity. The CMP process time window can be reduced by using a slurry which has a high oxide removal rate. This slurry should also have a low nitride removal rate in order to achieve local as well as global planarization at the same time. Therefore, a slurry with a high oxide:nitride selectivity is desired for STI applications.